-- Practice Midterm Solution Thread
Question 5: Daniel Pu and Andy Luong
Makefile is a build utility that defines a set of tasks to be executed on certain
files. They are also a simple way to organize code compilation as you can simply
type ‘make “task name”’ in the console within the correct directory, which will
execute the commands corresponding to the task for you.
Variables are names in the Makefile that represent a string(s) of text, which is
also known as the variable’s value. These variables along with their values can be
substituted within the rest of the Makefile as requests to targets, dependencies,
or commands. To use variables in make files, type a dollar sign with parentheses
or braces and in it is the variable name like $(objects). For notations, $@ refers
to the name of the target that is being generated, $< refers to the first
prerequisite of the target, and $^ refers to all prerequisites for the target.
An example program with more than one target and with a clean target in C can be the following:
objects = program.o foo.o utils.o
program : $(objects)
cc -o program $(objects)
$(objects) : defs.h
all: output main.o message.o
output: main.o message.o
gcc main.o message.o -o output
main.o: main.c
gcc -c main.c
message.o: message.c message.h
gcc -c message.c
clean:
rm -rf output
(
Edited: 2021-10-11)
<nowiki>Question 5: Daniel Pu and Andy Luong
Makefile is a build utility that defines a set of tasks to be executed on certain
files. They are also a simple way to organize code compilation as you can simply
type ‘make “task name”’ in the console within the correct directory, which will
execute the commands corresponding to the task for you.
Variables are names in the Makefile that represent a string(s) of text, which is
also known as the variable’s value. These variables along with their values can be
substituted within the rest of the Makefile as requests to targets, dependencies,
or commands. To use variables in make files, type a dollar sign with parentheses
or braces and in it is the variable name like $(objects). For notations, $@ refers
to the name of the target that is being generated, $< refers to the first
prerequisite of the target, and $^ refers to all prerequisites for the target.
An example program with more than one target and with a clean target in C can be the following:
objects = program.o foo.o utils.o
program : $(objects)
cc -o program $(objects)
$(objects) : defs.h
all: output main.o message.o
output: main.o message.o
gcc main.o message.o -o output
main.o: main.c
gcc -c main.c
message.o: message.c message.h
gcc -c message.c
clean:
rm -rf output
</nowiki>