Please post your solutions to the Mar 23 In-Class Exercise to this thread.

Best,

Chris

1. Each step has 2 map reduce rounds, therefore 20 map reduce rounds in 10 step PRAM computation along with 1 initial mapper that is input to step 1's reducer1.
2. There could be accumulators that hold a tuple (processor id, value) that could be shared between steps
3. LoadProcid k loads current processor id to the accumulator k

4.In each step, PRAM processors could be executing different instructions. Not every processor needs to be in sync with which map or reduce it's performing, there could be a counter which represents the status of map/reduce rounds and they could go to next step once the program counter indicates that 2 rounds of map-reduce is set to done.

1. It uses 20 map reduce roundsfor 10 PRAM processors.
2. LoadProcid k will load the processor's id to accumulator k
3. No, at a given timestamp, processors can be executing different instruction We would use a set of global registers which will store the program counters for each processor. Reducers will use these registers to find which instruction is the processor executing.

1. Each processor performs one step of computation with 2 map-reduce rounds, so we need 20 map-reduce rounds to simulate a 10-step PRAM computation.
2. To handle accumulators, we could reserve certain registers that can be read only by a particular processor and store any accumulated values of that processor in those registers.
3. To simulate the command LoadProcid k, we simply store the processor id in an accumulator k reserved to a particular processor.
4. In a given timestamp t, all PRAM processors are not doing the same instruction. Instead, the simulation uses a separate accumulator for each processor as a program counter to determine the current progress of the processor.

1. 2 rounds map-reduce for each processors per step, so total = 2*n = 20 (n=10)
2. We can use a group of registers only available to a processor for the computation.
3. To simulate Loadprocid() write to the register we are using like fake accumulators to store the processor id as (k,null)
4. In a given timestep t all PRAM processors are not doing the same instruction. The registers used as accumulators which are only used by particular processors only can be used to store the current step executed by a particular processor.

1. If we have 2 map reduce rounds per PRAM computation, then we have 20 map reduce rounds in a 10 step PRAM computation.
2. Accumulators can also have an address/value pair to represent where processor i writes into.
3. Reducer is operating on a (k, null) at the timestep. The processor id k will be written into an accumulator processor.
4. In a given timestamp, all PRAM processors do not need to be doing the same instruction. You can branch on different instructions based on processor id for example.

1. 20 map reduce rounds will be required for 10 step PRAM computation as 2 map reduce rounds are needed for every computation.<br>

2.Certain registers can be reserved to be used only by certain processors. <br>

1. LoadProcid k will store the processor id in accumulator k.<br>
2. In a given timestep t, not all PRAM processors will be doing the same instruction. They could be executing different ones.

1 - As there are 2 rounds for each processor per step, there will be 20 map-reduce rounds for a 10-step PRAM computation. 2 - We can reserve a specific group of registers only available to a processor for the computation. 3 - LoadProcid k will store processor id in accumulator k. 4 - In a given timestep t, all PRAM processors will not be working on the same instruction. Different instructions may be processed based on processor id.

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1. Apart from the initial Mapper and a probable final Reducer, taking 2 Mapper-Reducer combination per step, there will be 20 Map-Reduce rounds in a 10 step PRAM computation.
2. A group of registers can be used by a particular processor to store and read values to act an an accumulator. A particular group of registers can only be read and written into by a single processor.
3. A Reducer can write the processor id k into an accumulator as the reducers are operating on (k, null) at a timestep.
4. In a given timestep, all the PRAM processors may or may not be doing the same instruction. In the simulation, an accumulator is used to store the program counter per simulation of processor.

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1. As we require 2 rounds of map-reduce for each PRAM operation, total of 20 rounds of map-reduce will be required.
2. We can reserve a set of registers for each processor which can be used as accumulators
3. LoadProcId k can be used to store processor id in accumulator k
4. Each processor may not be executing the same instructions at a given timestamp. There could be a branching which can make processors out of sync

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