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2022-04-03

-- Mar 23 In-Class Exercise
1. 20 map-reduce rounds will be required for 10 step PRAM computation as each computation requires 2 map-reduce rounds. 2. Few of the registers can be used only by certain processors. 3. LoadProcid k will store the processor id in accumulator k. 4. In a given timestep t, not all PRAM processors will be doing the same instruction. They could be executing different ones.
1. 20 map-reduce rounds will be required for 10 step PRAM computation as each computation requires 2 map-reduce rounds. 2. Few of the registers can be used only by certain processors. 3. LoadProcid k will store the processor id in accumulator k. 4. In a given timestep t, not all PRAM processors will be doing the same instruction. They could be executing different ones.

-- Mar 23 In-Class Exercise
There will be 2 rounds (1 map, 1 reduce) per step of PRAM computation. Therefore, 20 map-reduce rounds will be required to simulate a PRAM computation. We can reserve a specific unique subset of registers for a given processor such that only that processor can access those registers. These registers will simulate accumulators. A reducer can write the processor id to an accumulator. No. In a given timestep t, different processors might not necessarily execute the same instruction because depending on the data, different processors might go down different paths in the execution flow.
There will be 2 rounds (1 map, 1 reduce) per step of PRAM computation. Therefore, 20 map-reduce rounds will be required to simulate a PRAM computation. We can reserve a specific unique subset of registers for a given processor such that only that processor can access those registers. These registers will simulate accumulators. A reducer can write the processor id to an accumulator. No. In a given timestep t, different processors might not necessarily execute the same instruction because depending on the data, different processors might go down different paths in the execution flow.

-- Mar 23 In-Class Exercise
1. There will be 2 rounds (1 map, 1 reduce) per step of PRAM computation. Sp 20 map-reduce rounds will be needed to simulate a PRAM computation. 2. We can reserve a specific unique subset of registers for a given processor such that only that processor can access those registers. These registers will simulate accumulators. 3. A reducer can write the processor id to an accumulator. 4. No. In a given timestep t, different processors might not necessarily execute the same instruction because depending on the data, different processors might go down different paths in the execution flow.
1. There will be 2 rounds (1 map, 1 reduce) per step of PRAM computation. Sp 20 map-reduce rounds will be needed to simulate a PRAM computation. 2. We can reserve a specific unique subset of registers for a given processor such that only that processor can access those registers. These registers will simulate accumulators. 3. A reducer can write the processor id to an accumulator. 4. No. In a given timestep t, different processors might not necessarily execute the same instruction because depending on the data, different processors might go down different paths in the execution flow.
2022-04-11

-- Mar 23 In-Class Exercise
1. In each PRAM computation two map reduce rounds would be taken, and so for 10 step PRAM computation, we will have 20 map reduce rounds. 
2. Accumulators can be handled by using a specific register to be only read by a particular processor and store any values of that processor within those registers. 
3. LoadProcid will store the processor id in the accumulator. 
4. Number of different processors might not do the same instruction in a given time step t. Depending on the date, they could follow different paths during the execution flow.
(Edited: 2022-04-11)
<pre> 1. In each PRAM computation two map reduce rounds would be taken, and so for 10 step PRAM computation, we will have 20 map reduce rounds. 2. Accumulators can be handled by using a specific register to be only read by a particular processor and store any values of that processor within those registers. 3. LoadProcid will store the processor id in the accumulator. 4. Number of different processors might not do the same instruction in a given time step t. Depending on the date, they could follow different paths during the execution flow. </pre>
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